A hard-bake process is used in conjunction with photolithography in semiconductor manufacturing….

A hard-bake process is used in conjunction with photolithography in semiconductor manufacturing. We wish to establish statistical control of the flow width of the resist in this process using and X and R charts. Twenty-five samples, each of size five wafers, have been taken when we think the process is in control. The specification limits on flow width are 1.50 ±0.50 microns. The interval of time between samples or subgroups is one hour. The flow width measurement data from these samples are shown in Table below. Wafers Sample Number 1 2 4 5 1.3235 14128 1.6744 1.4573 1.6914 2 1.4314 1.3592 1.6075 1.4666 1.6109 1.4284 1.4871 1.4932 1.4324 1.5674 1.5028 1.6352 1.3841 1.2831 1.5507 5 1.5604 1.2735 1.5265 1.4363 1.6441 1.5955 1.5451 1.3574 1.3281 L4198 7 1.6274 1.5064 1.8366 14177 1.5144 1.4190 L4303 1.6637 1.6067 1.5519 1.3884 17277 1.5355 1.5176 1.3688 10 1.4039 1.6697 1.5089 1.4627 1.5220 11 14158 1.7667 1.4278 1.5928 1.4181 12 1.5821 1.3355 1.5777 1.3908 1.7559 13 1.2856 14106 1.4447 1.6398 1.1928 14 14951 1.4036 1.5893 1.6458 1.4969 15 1.3589 1.2863 1.5996 1.2497 1.5471 16 1.5747 1.5301 1.5171 1.1839 1.8662 17 1.3680 1.7269 1.3957 1.5014 1.4449 18 1.4163 1.3864 1.3057 1.6210 1.5573 19 1.5796 14185 1.6541 1.5116 1.7247 1.7601 20 1.7106 1.4412 1.2361 1.3820 21 1.4371 1.5051 1.3485 1.5670 L4880 22 1.4738 1.5936 1.6583 1.4973 1.4720 23 1.5917 1.4333 1.5551 1.5295 1.6866 24 1.6399 1.5243 1.5705 1.5563 1.5530 25 1.5797 1.3663 1.6240 1.3732 1.6887 a. Is this process under SPC? (5 points) b. Is the process capable of meeting 4-sigma performance? (5 points) c. If the process is not, what percentage of the output will fall outside the specification limits?