A reconfigurable heterogeneous multicore chip adapts to the _current_ parallelism state (number of threads) of a running application by choosing which of its heterogeneous cores to use (power on). Each one of 10 alpha cores generates 6 TFs/s and dissipates 1 W. Each one of 40 beta cores generates 2.25 TF/s and dissipates 0.3 W. Our goal: Maximize aggregate chip performance, while not exceeding the power budget of 10 W. One core runs one thread (no multithreading). For each thread count below, fill
in the answers in the indicated spaces.
a) 10 threads: ____ alpha cores, ____ beta cores, _______ TFs/s, ____ W
b) 12 threads: ____ alpha cores, ____ beta cores, _______ TFs/s, ____ W
c) 14 threads: ____ alpha cores, ____ beta cores, _______ TFs/s, ____ W
d) 16 threads: ____ alpha cores, ____ beta cores, _______ TFs/s, ____ W
